The present invention relates to a semiconductor manufacturing technique, and in particular, to an effective technique applied to enhancement of the reliability of semiconductor devices having small semiconductor chips arranged at narrow pad pitches.
In Japanese Patent Laid-Open No. 8-116012, No. 5-160304, No. 5-36862, No. 11-289040, No. 11-514149, No. 7-153890, No. 6-291217 and No. 5-235246, there are disclosed techniques for fixing inner leads to metal sheets and ceramic sheets via adhesives or the like.
Firstly, in Japanese Patent Laid-Open No. 8-116012, there is disclosed a resin-sealing type semiconductor device in which an aluminum sheet is used as a heat radiation plate and the inner lead is fixed to the aluminum sheet via adhesives by providing an insulation layer on a surface of the aluminum sheet. There are described objects of improving heat-radiating properties, reducing material cost, and shortening manufacturing time.
In Japanese Patent Laid-Open No. 5-160304, there is disclosed a semiconductor device having a construction in which an aluminum sheet is used as a heat radiation plate and leads are affixed to the aluminum sheet via adhesives as an object of improving heat properties.
In Japanese Patent Laid-Open No. 5-36862, there is disclosed a semiconductor device having a construction in which a ceramic sheet is affixed to inner leads. Heat generated from semiconductor chips is discharged into the exterior thereof through ceramic sheets and inner leads to thereby improve heat-radiating properties of the semiconductor device.
In Japanese Patent Laid-Open No. 11-289040, there are disclosed lead frames to which inner leads are joined at one surface of a heat radiation plate through an electrical insulation layer and adhesive layer, and a semiconductor device using these lead frames. There are described objects of improving the quality and reducing the manufacturing cost thereof.
In Japanese Patent Laid-Open No. 11-514149, there is disclosed an electronic package having a construction in which semiconductor chips and leads are fixed to a heat slug, on the surface of which electric insulating anode treated coating is provided. There is described an object of improving the heat properties thereof.
In Japanese Patent Laid-Open No. 7-153890, there is disclosed a lead frame for a semiconductor device in which inner leads are fixed to heat radiation plates via adhesives, the heat radiation plates each comprising a metal sheet on which insulation treatment is treated. There are described objects of attaining improvement of heat radiating properties, high speed of signal processing, and long life of the semiconductor device by this lead frame.
In Japanese Patent Laid-Open No. 6-291217, there is disclosed a heat-dissipation type lead frame in which a ceramic sheet is used as a heat radiation plate and inner leads are fixed to this ceramic plate via adhesives. There are described objects of not only suppressing residual stress generated by heat but also preventing a shape of the frame from being deformed at the manufacturing stages thereof when this lead frame has a package structure.
In Japanese Patent Laid-Open No. 5-235246, there is disclosed a semiconductor device of a construction in which a main surface of each semiconductor chip is fixed to one surface of an insulation tape via adhesives, and each inner lead is fixed to the other surface via the adhesives, and each semiconductor chip surface electrode is exposed from each hole of a insulation tape to connect the inner leads and the surface electrodes via said holes by wires. There are described objects of increasing the degree of design freedom of chips and attaining high speed of signal transmission.
However, techniques described in the above-mentioned seven Japanese Patent Laid-Open references except for Japanese Patent Laid-Open No. 5-235246 have objects of improving heat radiation properties thereof by using metal sheets or ceramic sheets, and do not disclose the concept that a technique for fixing inner leads to metal sheets or ceramic sheets via adhesives is used for semiconductor devices having many pins and narrow pad pitches.
In addition, in Japanese Patent Laid-Open No. 5-235246, there is disclosed a technique for fixing inner leads to an insulation tape. But, in the construction (the construction in which the main surface of the semiconductor chip is fixed to one surface of the insulation tape, and the inner lead is fixed in the other surface thereof, and the pads of the semiconductor chip are exposed from the holes of the insulation tape to connect the inner leads and pads via said holes by the wires) described therein, there arise problems of decrease in the tape area on each chip and in area for forming the holes in the insulating tape if the semiconductor chip becomes small and has many pins.
Consequently, there arises a problem of difficulty in attaining a structure having small chips and many pins on the basis of the structure disclosed in Japanese Patent Laid-Open No. 5-235246.
Furthermore, in the construction disclosed in Japanese Patent Laid-Open No. 5-235246, since holes must be formed in the insulation tape, the insulation tape having a size fitted to the chip size is required and lead frame to which this insulation tape is affixed must be prepared. And so, there arises a problem of no attainment of standardization of the lead frame.
Accordingly, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof which are capable of achieving narrow pad pitches and improvement of the reliability.
Another object of the present invention is to provide a semiconductor device and a manufacturing method thereof that allow the lead frame to be standardized.
The above-mentioned and other objects and new features of the present invention will become apparent from the detailed description of the present specification and the accompanied drawings.
Of the inventions to be disclosed in the present application, outlines of typical inventions will be briefly described as follows.
That is, the semiconductor device that is the present invention comprises a plurality of inner leads extending around a semiconductor chip; a thin sheet-shaped insulating member supporting said semiconductor chip and joined to an end portion of said respective inner leads; a bonding wire for connecting surface electrodes of said semiconductor chip and said inner leads corresponding thereto; a seal portion formed by resin-sealing said semiconductor chip, said wire and said insulating member; and a plurality of outer leads linked to said inner leads and exposed from said seal portion, wherein a length of a shorter side of a main surface of said semiconductor chip formed in a quadrilateral shape is twice or less than a distance from a tip of the inner leads arranged at the farthest location from a center line of the semiconductor chip in a plane direction, to said semiconductor chip.
According to the present invention, it is possible to certainly have effects on suppression of wire flow caused by flow of mold resin, and of flapping of the inner leads, by fixing the inner leads to the insulating member.
As a result, it is possible to improve reliability of the semiconductor device having a construction in which the inner leads are joined to the insulating member.
Further, it is possible to mount the semiconductor chip to the insulating member even if a chip becomes small in size, and it is no longer necessary to prepare the lead frame per size of a chip. As a result, standardization of the lead frame can be attained.
In addition, the semiconductor device that is the present invention comprises a plurality of inner leads extending around a semiconductor chip; a thin sheet-shaped insulating member supporting said semiconductor chip and joined to an end portion of said respective inner leads: a bonding wire for connecting surface electrodes of said semiconductor chip and said inner leads corresponding thereto; a seal portion formed by resin-sealing said semiconductor chip, said wire and said insulating member; and a plurality of outer leads linked to said inner leads and exposed from said seal portion, wherein a length of a shorter side of a main surface of said semiconductor chip formed in a quadrilateral shape is longer than a distance from a tip of the inner leads arranged at the farthest location from a center line of the semiconductor chip in a plane direction, to said semiconductor chip, and is twice or less than this distance.
Further, the semiconductor device that is the present invention comprises a plurality of inner leads extending around a semiconductor chip; a thin sheet-shaped insulating member supporting said semiconductor chip and joined to an end portion of said respective inner leads; an adhesive layer for joining said inner leads and said insulating member; a bonding wire for connecting surface electrodes of said semiconductor chip and said inner leads corresponding thereto; a seal portion formed by resin-sealing said semiconductor chip, said wire and said insulating member; and a plurality of outer leads linked to said inner leads and exposed from said seal portion.
According to the present invention, it is possible to suppress wire flow caused by flow of mold resin and/or flapping of the inner leads. As a result, a narrow pad pitch of the inner leads can be attained.
Further, it is possible to suppress expansion and shrinkage of respective tips of the inner leads at the time of solder reflow generated by thermal expansion coefficient differences between mold resin and the inner leads.
This can prevent disconnection generated in joining portions between the wires and the inner leads. As a result, reliability of the semiconductor device can be improved.
Moreover, in the semiconductor device that is the present invention, the semiconductor chip is thicker than a total of the insulating member and the adhesive layer in thickness.
According to the present invention, since thickness of the insulating member can be made thin, the thermal conduction can be improved at the time of die bonding.
In addition, since the thickness of the insulating member can be made thin, the semiconductor device can be formed in a thin shape. This can reduce material cost thereof, and attain low cost of semiconductor device.
The manufacturing method of a semiconductor device that is the present invention comprises the steps of: preparing a multi-link lead frame formed by linking in a line with a plurality of package areas, each of the package areas including a plurality of inner leads, a thin sheet-shaped insulating member joined to an end portion of each of said inner leads and capable of supporting a semiconductor chip; mounting said semiconductor chip on said insulating member in each of said package area; connecting surface electrodes of said semiconductor chips and said inner leads corresponding thereto by a wire; forming a seal portion by resin-sealing said semiconductor chips, said wire, and said insulating member; and separating a plurality of outer leads exposed from said seal portion, from a frame section of said lead frame.
Further, the manufacturing method of a semiconductor device that is the present invention comprises the steps of: preparing a matrix frame formed by arranging a plurality of package areas in a matrix arrangement, each of the package areas including a plurality of inner leads, a thin sheet-shaped insulating member joined to an end portion of each of said inner leads and capable of supporting a semiconductor chip; mounting said semiconductor chip on said insulating member in each of said package area; connecting surface electrodes of said semiconductor chips and said inner leads corresponding thereto by a wire; forming a seal portion by resin-sealing said semiconductor chips, said wire, and said insulating member; and separating a plurality of outer leads exposed from said seal portion, from a frame section of said matrix frame.